One known method of forming a laminate circuitized substrate (e.g., PCB) structure includes forming layers of dielectric material and electrically conducting material to provide multiple layers of circuits and voltage planes. Circuits can be discrete wiring patterns known as signal planes. Voltage planes can be either ground plane or power planes, and are sometimes collectively referred to as power planes. In one technique of forming such structures, layers of dielectric material and conductive material are successively applied, e.g., the dielectric material is applied and then circuits or voltage planes are provided thereon and, typically, thru-holes (described in greater detail hereinbelow) are formed, typically by drilling or etching. This method relies on each successive step of adding additional structure and the circuitry layers are formed individually, e.g., in each step in forming the plane having circuit traces or formed power planes. This requires precision drilling to form the plated thru-holes (PTHs) all of which is time consuming, especially where there are a large number of drilled holes required to form PTHs.
More recently, methods have been described that provide a relatively inexpensive photolithographic technique of forming a composite laminate structure (substrate assembly) from individual discrete laminate structures (substrates). For example, see U.S. application Ser. No. 09/812,261, entitled “Printed Wiring Board Structure With Z-Axis Interconnections” and filed Mar. 19, 2001. See also U.S. Pat. No. 6,388,204 (Lauffer et al) and U.S. Pat. No. 6,479,093 (Lauffer et al), the teachings of which are incorporated herein by reference.
In double-sided and multilayer PCBs, it is necessary to provide the aforementioned thru-holes between the various conductive layers or sides of the board. This is commonly achieved by providing metallized, conductive thru-holes in the board which communicate with the sides and layers requiring electrical interconnection. For some applications, it is desired that electrical connection be made with almost if not all of the conductive layers. In such a case, thru-holes are also typically provided through the entire thickness of the board. For these, as well as other applications, it is often desired to also provide electrical connection between the circuitry on one face of the board and one or more of the inner circuit layers. In those cases, “blind vias”, passing only part way through the board are provided. In still another case, such multilayered boards often require internal “vias” which are located entirely within the board's structure and covered by external layering, including both dielectric and conductive. Such internal “vias” are typically formed within a sub-part structure of the final board and then combined with other layers during final lamination of the board. For purposes of this application, therefore, the term “thru-hole” is meant to include such conductive openings that pass entirely through the board (plated through holes or PTHs), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as “internal vias” which is internally “captured” by the board's outer layers.
Complexity of circuitized substrates such as PCBs has increased significantly over the past few years, due primarily to increased operational requirements for the products in which these substrates are utilized. For example, boards for mainframe computers may have as many as thirty-six layers of circuitry or more, with the complete stack having a thickness of about 0.250 inch (or 250 mils). These boards are typically designed with three or five mil wide signal lines and twelve mil diameter thru-holes. For increased densification in many of today's PCBs, the industry seeks to reduce signal lines to a width of two mils or less and thru-holes to a diameter of two mils or less. As will be defined herein in greater detail, a primary feature of the instant invention is the provision of a circuitized substrate possessing much greater operational capabilities than such substrates and electrical assemblies utilizing same known in the art. A specific feature of the invention is the inclusion of one or more organic memory “devices” within the substrate itself, thereby eliminating the need for externally mounted components of this type and saving more surface space for components such as semiconductor logic chips and the like to even further increase the final product's operational capabilities.
In U.S. Pat. No. 6,704,207, entitled “Device and Method for Interstitial Components in a Printed Circuit Board”, issued Mar. 9, 2004, there is described a printed circuit board (PCB) which includes a first layer having first and second surfaces, with an above-board device (e.g., an ASIC chip) mounted thereon. The PCB includes a second layer having third and fourth surfaces. One of the surfaces can include a recessed portion for securedly holding an interstitial component. A “via”, electrically connecting the PCB layers, is also coupled to a lead of the interstitial component. The described interstitial components include components such as diodes, transistors, resistors, capacitors, thermocouples, and the like. In what appears to be the preferred embodiment, the interstitial component is a resistor having a similar size to a “0402” resistor (manufactured by Rohm Co.), which has a thickness of about 0.014 inches.
In U.S. Pat. No. 6,242,282, entitled “Circuit Chip Package and Fabrication Method”, issued Jun. 5, 2001, there is described a method for packaging a chip which includes the steps of providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, a substrate via extending from the first side to one of the second side metallized portions, and a chip via extending from the first side to the second side non-metallized portion. The method also includes positioning a chip on the second side with a chip pad of the chip being aligned with the chip via, and patterning connection metallization on selected portions of the first side of the interconnect layer and in the via so as to extend to the second side metallized portion and to the chip pad. About the chip is molded a “substrate” or other dielectric material.
In U.S. Pat. No. 6,084,306, entitled “Bridging Method of Interconnects for Integrated Circuit Packages”, issued Jul. 4, 2000, there is described an integrated circuit package having first and second layers, a plurality of routing pads being integral with the first layer, a plurality of upper and lower conduits, respectively, disposed on the upper and lower surfaces of the first layer, one of the upper conduits electrically connected to one of the lower conduits, a plurality of pads disposed on the second layer, vias that electrically connect the pads to the lower conduits and a chip adhered to the second layer having bonding pads, at least one of which is electrically connected to one of the routing pads.
In U.S. Pat. No. 5,831,833, entitled “Bare Chip Mounting Printed Circuit Board and a Method of Manufacturing Thereof by Photo-etching”, issued Nov. 3, 1998, there is described a method of manufacturing a “bare chip” multi-layer printed circuit board in which arbitrary numbers of wiring circuit conductor layers and insulating layers are alternately stacked on one or both surfaces of a printed circuit board as a substrate, and a recessed portion with an upper opening capable of mounting and resin-encapsulating a bare chip part is formed on the surface of the printed circuit board. In what appears to be the preferred embodiment, one of the insulating layers is made from a photosensitive resin, and the bare chip part mounting recessed portion is formed by photo-etching the insulating layer made from the photosensitive resin.
In U.S. Pat. No. 5,426,263, entitled “Electronic Assembly Having a Double-sided Leadless Component”, issued Jun. 20, 1995, there is described an electronic assembly which has a double-sided leadless component and two printed circuit boards. The component has a plurality of electrical terminations or pads on both opposing major surfaces. Each of the printed circuit boards has a printed circuit pattern that has a plurality of pads that correspond to the electrical terminations on both sides of the double-sided leadless component. The electrical terminals on one side of the component are attached to the pads on the first board and the electrical terminals on the other side of the leadless component are attached to the pads on the second board. The printed circuit boards are joined together to form a multilayered circuit board so that the double-sided leadless component is buried or recessed inside. The component is attached to the pads of the printed circuit board using solder.
In U.S. Pat. No. 5,280,192, entitled “Three-dimensional Memory Card Structure With Internal Direct Chip Attachment”, issued Jan. 18, 1994, there is described a card structure which includes an internal three dimensional array of implanted semiconductor chips. The card structure includes a power core and a plurality of chip cores. Each chip core is joined to the power core on opposite surfaces of the power core, and each chip core includes a compensator core having a two dimensional array of chip wells. Each chip well allows for a respective one of the semiconductor chips to be implanted therein. Further, a compliant dielectric material is disposed on the major surfaces of the compensator core except at the bottoms of the chip wells. The compliant dielectric material has a low dielectric constant and has a thermal coefficient of expansion compatible with those of the semiconductor chips and the compensator core, so that thermal expansion stability with the chips and the compensator core is maintained.
In U.S. Pat. No. 5,099,309, entitled “Three-dimensional Memory Card Structure With Internal Direct Chip Attachment”, issued Mar. 24, 1992, there is described a memory card structure containing an embedded three dimensional array of semiconductor memory chips. The card structure includes at least one memory core and at least one power core which are joined together in an overlapping relationship. Each memory core comprises a copper-invar-copper (CIC) thermal conductor plane having a two dimensional array of chip well locations on each side of the plane. Polytetrafluoroethylene (PTFE) covers the major surfaces of the thermal conductor plane except at the bottoms of the chip wells. Memory chips are placed in the chip wells and are covered by insulating and wiring levels. Each power core comprises at least one CIC electrical conductor plane and PTFE covering the major surfaces of the electrical conductor plane. Provision is made for providing electrical connection pathways and cooling pathways along vertical as well as horizontal planes internal to the card structure.
In U.S. Pat. No. 5,016,085, entitled “Hermetic package for integrated circuit chips, issued May 14, 1991, there is described a hermetic package which has an interior recess for holding a semiconductor chip. The recess is square and set at 45 degrees with respect to the rectangular exterior of the package. The package uses ceramic layers which make up the package's conductive planes with the interior opening stepped to provide connection points. The lowest layer having a chip opening therein may be left out of the assembly to provide a shallower chip opening recess.
In U.S. Pat. No. 4,956,694, entitled “Integrated circuit chip stacking”, issued Sep. 11, 1990, there is described a device for increasing the density of integrated circuit chips on a printed circuit board. A plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board. Each of the input/output data terminals, power and ground terminals of the chips are connected in parallel. Each chip is individually accessed by selectively enabling the desired chip.
It is thus seen from the above patents that various methods have been implemented for more closely “bonding” electronic components such as semiconductor chips and a substrate as one integral assembly, including the use of chip “recesses” with an appropriate cover or like material and, more specifically, as seen in two of these patents (U.S. Pat. Nos. 5,099,309 and 5,280,192), use of internal chip placement and coupling amongst the substrate's layered structure itself.
As understood from the following, the present invention represents a significant advancement over the above structures and methods by providing a circuitized substrate in which one or more organic memory devices are integrally formed as part of the substrate's mutilayered structure and capable of effectively operating in conjunction with other components such as logic semiconductor chips located externally of the substrate. The formed substrate assures effective coupling of the integrally formed memory devices to conductive layers (e.g., signal lines, power or ground planes, etc.) of the substrate while also assuring optimum heat removal so as to maintain long component life. The invention is able to do so expeditiously in such a manner that the method of forming the substrate can be carried out using many known PCB manufacturing processes with little modification thereto, thus assuring a final product without a corresponding relatively high price tag.
The invention so defined is also able to provide internal memory devices capable of being electrically coupled to such external components as a logic semiconductor chip with little or no signal “noise” and with significantly reduced impedance. In general, any structure that allows a signal to propagate from one point to another may be defined as a transmission line (in a PCB, such a line may be referred to as a “trace” if part of a substrate conductive layer, a plated “thru-hole” (PTH) if rendered conductive (e.g., plated with a metal such a copper), or even a conductive plane (e.g., power or ground) if in substantially solid, planar configuration. As a signal propagates along this line, both voltage and current are present. The ratio of these two parameters is defined as the characteristic impedance of the line which is a property determined solely by the material and geometry of the line. The characteristic impedance is proportional to the ratio of the inductance and capacitance of the line. In general, impedance is dependent upon frequency, but for lines that are essentially lossless, it can be considered constant. In signal lines, including PTHs for coupling “traces” with other “traces” on different conductive layers, ideally the signal arriving at the receiving end will be the same as that which entered the line at the driver end. However, if the transmission line changes characteristic impedance at any point along the way, signal behavior becomes more complicated. At the interface where such an impedance change occurs, partial reflections of the signal will be created. These reflected waves will travel back toward the source for possible reflection a second time. At each interface where an impedance change occurs, a reflected signal will thus be created. The reflections caused by these impedance mismatches have the ability to alter the original signal transmission, even possibly causing such problems as logic circuits to switch inadvertently. Furthermore, as signal “rise times” drop below a certain level (in highly dense PCB structures, 1 nanosecond (ns)), PCB thru-holes, including the relatively short internal “vias” mentioned above, may possibly create large enough reflections as to potentially cause significant signal transmission concerns. Consequently, as clock rates increase and signal rise times become short, as is currently being demanded in many of today's products, all portions of the interconnection path need to be well matched to the impedances of the other parts of the substrate and to the electronic components these lines interconnect. With particular attention to internal or other “vias” (as stated, all referred to as thru-holes herein), the capacitance created is by way of a stray electric field present between the via and the various power, ground or signal layers in the PCB. The inductance of the via is related to the magnetic field surrounding the portion of the via carrying the signal current. Typically, the inductance of the via is quite small relative to its capacitance. As such, most vias exhibit very low impedance and are a poor match to typical PCB traces. Reducing the via's capacitance or increasing the via's inductance will raise the via's impedance and create an improved match. This improvement will improve the capability to carry higher data rates from the internally positioned chip(s) through the via(s) to the substrate's external surfaces and thus to external components coupled to the substrate. The unique structure of the instant invention is able to provide effective coupling between an internal memory device and an external semiconductor chip or the like while substantially overcoming the aforementioned problems associated with other structures.
It is believed that such a substrate, method of making same, and various products utilizing same will constitute significant advancements in the art.